In order to enhance the operation of the microprocessor, a pipelined architecture may be used. In a pipelined architecture, the output of the microcode ROM is stored in a latch. Hence, the output of the latch is one instruction cycle behind the output of the microcode ROM. While pipelining has significant advantages to the overall operation of the circuit, one detriment of pipelining is its effect on conditional jump instructions. In a conditional jump instruction, a jump to a specified address is contingent upon whether a specified condition is met. In a pipelined architecture, the next instruction will be output from the microcode ROM as the condition is being evaluated.
Consequently, after a conditional jump instruction, the next sequential instruction in the microcode ROM will be executed, whether or not the condition is met. The next instruction after a conditional jump instruction is known as the "deadbox". In some instances, the microcode programmer may be able to make use of the deadbox. Most often, however, a NOP instruction is placed in the deadbox.
In microcode programming, it is often desirable to check a number of conditions. Ideally, a series of conditional jumps would be placed one after the other in the microcode ROM. However, because of the pipelined architecture, the ramifications of a series of conditional jumps is often very complex. The alternative would be to place NOPs in the deadboxes, thereby having a conditional jump every other memory location. This technique, however, is very slow.
Therefore, a need has arisen in the industry to provide a sequencing architecture which enhances the performance of a series of conditional jumps.